In logic circuit design, it is known that under certain conditions the outputs of logic devices will assume unknown states for short periods of time. For example, if a logic gate has output different rise and fall delays, then it is possible for the output to contain spikes, or glitches. This problem has been known for some time now in the logic circuit simulation art. It has been quite expensive in terms of run time overhead to provide spike analysis in logic simulators. In most cases, the problem is handled in one of two ways. One solution is to ignore the problem. In this case, the problem does not occur during simulation. This solution results in an overly optimistic simulation in which such spikes might occur in practice, but in which the designer has no indication during simulation and design of the potential problem. The other solution is to assume that fully developed output pulses develop at the output of a device in response to every impulse, irrespective of the duration of the input pulse. This solution is overly pessimistic. The two solutions are sometimes referred to as the pulse suppress and pulse pass modes of simulation, respectively.
As mentioned, the need and methods for performing spike analysis have been known in the logic simulation art for some time. U.S. Pat. No. 4,787,062 to Nei, et al discusses one solution in the context of a hardware simulator. In brief, the method used to perform spike analysis in the patent is as follows. If the spike analysis mode is in effect for a device when an input event is scheduled for the device, then an event queue is searched and if there are other events scheduled in an event queue for the device, an appropriate output register is forced to a state defined as UNKNOWN. However, as mentioned, the overhead in terms of simulation time to perform this analysis, can become quite large.